The present invention relates to a semiconductor device and, more particularly, to a semiconductor device fabricated on a multiple substrate and a method for fabricating the same.
A merged memory and logic (MML) device is as an example of a semiconductor device formed on a multiple substrate. The merged memory and logic device has a memory device, such as DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory) or the like, and a logic device, which are formed on the multiple substrate in order to achieve a system marked by lightness, thinness, shortness, smallness, high efficiency and low-power consumption.
FIGS. 1A to 1C are cross-sectional views showing fabrication processes of a merged memory and logic device according to the prior art.
As shown in FIG. 1A, an interlayer insulating layer 11 is formed on a memory device (not shown) and a first semiconductor substrate 10. A final metal wire is formed on the interlayer insulating layer 11 and then bonding pads 12 are formed in order to join a second semiconductor substrate to the first semiconductor substrate 10. A protection layer 13 is formed on the bonding pads 12 and the interlayer insulating layer 11 and then the bonding pads 12 are exposed by selectively etching back the protection layer 13. Typically, different elements, such as gate electrodes of transistors, bit lines, metal wires, contact holes and via holes, are formed on the first semiconductor substrate 10 and metal lines and polysilicon layers are used to implement these structures.
On the other hand, referring to FIG. 1B, an interlayer insulating layer 21 is formed on a logic device (not shown) which is formed on a second semiconductor substrate 20. A final metal wire is formed on the interlayer insulating layer 21 and bonding pads 22 are formed on the interlayer insulating layer 21 in order to join the second semiconductor substrate 20 to the first semiconductor substrate 10. A protection layer 23 is formed on the bonding pads 22 and the interlayer insulating layer 21 and then the bonding pads 22 are exposed by selectively etching back the protection layer 23.
The interlayer insulating layer 21 is formed on logic transistors made by polysilicon layers, multi-step metal wires and contact and via holes for metal interconnection.
As shown in FIG. 1C, in order to connect each memory device and logic device formed on the first semiconductor substrate 10 and the second semiconductor substrate 20, respectively, the second semiconductor is turned upside down so as to join the bonding pads 12 of the first semiconductor substrate 10 to the bonding pads 22 of the second semiconductor substrate 20 and the first and second semiconductors 10, 20 are stacked. When the stacked first and second semiconductor substrates 10, 20 are annealed at a temperature of 300xc2x0 C. to 450xc2x0 C., the bonding pads 12 of the first semiconductor 10 and the bonding pads 22 of the second semiconductor 20 are electrically connected.
Since a conventional stacking technique for a merged memory and logic device, as mentioned above, does not use a mask align key for joining the first and second semiconductor substrates 10 and 20, a misalignment is caused, making it difficult to electrically connect the first semiconductor substrate 10 and the second semiconductor substrate 20.
It is, therefore, an object of the present invention to provide a semiconductor device fabricated on multiple substrates and a method for fabricating the same.
In accordance with a first aspect of the present invention, there is provided a semiconductor device, comprising: 1) a first structure including a first semiconductor substrate, at least one first bonding pad, and at least one alignment key formed on the first semiconductor substrate; and 2) a second structure including a second semiconductor substrate, at least one second bonding pad, and at least one alignment aperture passing through the second semiconductor substrate.
In accordance with another aspect of the present invention, there is provided a semiconductor device comprising: 1) a first structure including a first semiconductor substrate having a first circuit device, a first interlayer insulating layer formed on the first semiconductor substrate, at least one first bonding pad formed on the first interlayer insulating layer, and at least one alignment key formed on the first interlayer insulating layer; and 2) a second structure including a second semiconductor substrate having a second circuit device, a second interlayer insulating layer formed on the second semiconductor substrate, at least one second bonding pad formed on the second interlayer insulating layer, and at least one beam guiding aperture passing through the second structure and providing a beam path to the alignment key on the first interlayer insulating layer.
In accordance with a further aspect of the present invention, there is provided a method for fabricating a semiconductor device, comprising steps of providing a first semiconductor substrate having a first circuit device; forming a first interlayer insulating layer on the first semiconductor substrate; forming at least one bonding pad on the first interlayer insulating layer; forming at least one alignment key on the first interlayer insulating layer; providing a second semiconductor substrate having a second circuit device; forming a second interlayer insulating layer on the second semiconductor substrate; forming at least one second bonding pad on the second interlayer insulating layer; forming at least one alignment aperture by selectively etching the second interlayer insulating layer and the second semiconductor substrate; aligning the first semiconductor substrate and the second semiconductor substrate for joining the first bonding pad with the second bonding pad; irradiating a beam passing through the alignment aperture and detecting a beam reflectivity; re-aligning the first semiconductor substrate until the beam reflectivity is matched with a reflectivity of the alignment key; and joining the first bonding pad with the second bonding pad by a thermal treatment process.